TXFULLF=0, SPMF=0, MODF=0, RFIFOEF=0, RNFULLF=0, TNEAREF=0, SPTEF=0, SPRF=0
SPI Status Register
| RFIFOEF | SPI read FIFO empty flag 0 (0): Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO. 1 (1): Read FIFO is empty. |
| TXFULLF | Transmit FIFO full flag 0 (0): Transmit FIFO has less than 8 bytes 1 (1): Transmit FIFO has 8 bytes of data |
| TNEAREF | Transmit FIFO nearly empty flag 0 (0): Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit 1 (1): Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit |
| RNFULLF | Receive FIFO nearly full flag 0 (0): Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits (when C3[RNFULLF_MARK] is 1) 1 (1): Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1) |
| MODF | Master Mode Fault Flag 0 (0): No mode fault error 1 (1): Mode fault error detected |
| SPTEF | SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled) 0 (0): SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1) 1 (1): SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1) |
| SPMF | SPI Match Flag 0 (0): Value in the receive data buffer does not match the value in the MH:ML registers 1 (1): Value in the receive data buffer matches the value in the MH:ML registers |
| SPRF | SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled) 0 (0): No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1) 1 (1): Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1) |